Methods and apparatus for byte alignment operations for a memory device that stores an odd number of bytes

ABSTRACT

A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte; count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading. An arbiter receives the cell available signals, and it generates control signals to select one of the FIFO memory cores. An output selection circuit utilizes the control signals to output data from one of the FIFO memory cores. The FIFO memory device further includes a plurality of output pins that receive the cell available signals and that receive the cell size information.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention is directed toward the field of memory, andmore particularly to a first-in-first-out (FIFO) memory device thatincludes programmable cell sizes and multiplexing among FIFO memorycores.

[0003] 2. Art Background

[0004] There are many types of memory devices that are used to storedata. One type of memory device is known as a first-in-first-out (FIFO)memory or buffer. In a FIFO memory, data is stored in a sequential orderas data is written to the device. Typically, FIFO devices maintain awrite pointer that specifies the location or address to write the nextdata entry into the FIFO. For each write operation, the write pointer isincremented. The FIFO memory is sequentially read in the same order asit was written. Typically, to implement a read operation, a read pointeris maintained, and the read pointer is incremented for each subsequentread operation. Thus, the data that is first written to the FIFO deviceis also the data that is first read from the FIFO device.

[0005] FIFO memories have many uses in circuit applications. Forexample, FIFOs may be used as a queue for storing packets of data in anetwork device. For the network application, data packets are stored inthe FIFO in the sequential order that they are written. For routing ordistribution, the data packets are sequentially read starting with thefirst data packets written.

[0006] A specification, known as the universal test and operationphysical (PHY) interface for asynchronous transfer mode (ATM) or theUTOPIA specification, defines an interface between the ATM physicalmedia layer and the ATM layer itself. As set forth in the UTOPIAspecification, the storage of data in the FIFO device may be arranged incells. In this configuration, sequential write operations are executedto fill an entire cell with data. Similarly, sequential read operationsare executed on a cell to read all data stored in that cell. The UTOPIAspecification specifies a cell size of 53 bytes per cell. Although the53 bytes per cell may be suited for certain applications, otherapplications, such as different network standards that use differentpacket sizes, may be suited for different cell sizes. The ability toselect the number of bytes per cell provides a more flexible FIFO devicethat may be suited for more applications. For example, a device may beconfigured to permit the selection of a wide range of cell sizes.Consequently, it is desirable to develop a FIFO memory that permits auser to specify a cell size by selecting the number of bytes for eachcell.

SUMMARY OF THE INVENTION

[0007] A variable cell size circuit supports user programmable cellsizes in a memory device. The variable cell size circuit includes acounter and a comparator, and it controls successive accesses to a cellin the memory device. The comparator receives a cell size value thatspecifies the number of bytes for the current cell. The countergenerates a count that specifies a number of accesses to the cell, andthe comparator compares the count with the cell size value. In addition,the comparator resets the counter when the count equals the cell sizevalue to initialize the circuit for a subsequent access operation. Inone embodiment, the memory comprises a first-in-first-out (FIFO) memory,and the access operations include read and write operations to the cell.The variable cell size circuit further includes a prediction circuitthat indicates completion of access to the cell a predetermined numberof counts prior to completion of the actual access.

[0008] In one embodiment, the FIFO memory device supports a one bytewrite operation and a two byte read operation. For this embodiment, analignment circuit generates data for write operations in cells thatstore an odd number of bytes per sell to compensate or align for the twobyte per cell read operations. Specifically, the alignment circuitprograms predetermined data into an additional byte position, during abyte insertion operation, and it programs over a previously written byteposition in a byte deletion operation.

[0009] In one embodiment, the first-in-first-out (FIFO) memory deviceincludes a plurality of FIFO memory cores that contain a plurality ofcells. Each FIFO memory core includes a circuit that generates a cellavailable signal to indicate whether a cell in a corresponding FIFOmemory core is available for reading. An arbiter receives the cellavailable signals, and it generates control signals to select one of theFIFO memory cores. An output selection circuit utilizes the controlsignals to output data from one of the FIFO memory cores. In oneembodiment, the arbiter contains a round robin sequencer for selecting aFIFO memory core with a cell available in a sequential order. The FIFOmemory device further includes a plurality of output pins that receivethe cell available signals and that receive a prediction signal. Thus,the cell available information and the prediction signal are outputexternally from the FIFO device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a block diagram illustrating one embodiment for a FIFOdevice that has programmable cell sizes and optimal cell selectionfunctions.

[0011]FIG. 2 is a block diagram illustrating a FIFO block configured inaccordance with one embodiment of the present invention.

[0012]FIG. 3 is a block diagram illustrating a variable cell sizecircuit to define the number of bytes per cell.

[0013]FIG. 4 illustrates one embodiment of a write variable cell sizecircuit.

[0014]FIG. 5 illustrates one embodiment for a read variable cell sizecircuit.

[0015]FIG. 6 is a block diagram of a cell in a memory core that has beenprogrammed to include nine bytes per cell.

[0016]FIG. 7 illustrates one embodiment for a circuit to generate amemory address for a write operation that executes alignment operations.

[0017]FIG. 8 is a timing diagram illustrating the loading of a MUX forthe output selection circuit.

[0018]FIG. 9 is a state diagram illustrating one embodiment for anarbiter that selects among FIFO memory cores.

[0019]FIG. 10 illustrates one embodiment for a circuit that receivescell size programming information and that transmits cell availableinformation.

[0020]FIG. 11 illustrates one embodiment for expanding the output databus.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021]FIG. 1 is a block diagram illustrating one embodiment for a FIFOdevice that has programmable cell sizes and optimal cell selectionfunctions. A first-in-first-out (FIFO) device 100 contains a pluralityof FIFO memory blocks (FIFO A, FIFO B, FIFO C, and FIFO D) labeled 130,135, 140 and 145, respectively. Although the embodiment for the FIFOdevice 100 shown in FIG. 1 includes four FIFO memory blocks, any numberof FIFO memory blocks may be used without deviating from the spirit andscope of the invention. In one embodiment, the FIFO device 100 isimplemented on an integrated circuit (IC) device. The FIFO device 100further includes an arbiter 150 and an output selection circuit 155. Ingeneral, the arbiter 150 and output selection circuit 155 select data,from one of the FIFO memory blocks (FIFO A 130, FIFO B 135, FIFO C 140,and FIFO D 145), and they transmit data to an external output device.

[0022] In FIG. 1, a number of external devices are shown coupled theFIFO device 100. A plurality of physical devices, labeled PHY#1 105,PHY#2 110, PHY#3 115, and PHY#4 120 are coupled to the FIFO device 100at memory block FIFO A 130, memory block FIFO B 135, memory block FIFO C140, and memory block FIFO D 145, respectively. In one embodiment, eachphysical device transmits data to a memory block in accordance with theUTOPIA specification. As shown in FIG. 1, each interface includes a ninebit data bus (RXDataA[8:0], RXDataB[8:0], RXDataC[8:0], andRXDataA[8:0]), and control signals (Cntl). During a write operation,nine bits of data are input from each physical device to a FIFO memoryblock.

[0023] For purposes of explanation, the output of the FIFO device 100 isshown coupled to an asynchronous transfer mode (ATM) device 125. Inaccordance with the UTOPIA specification, the FIFO device 100, throughuse of the arbiter 150 and output selection circuit 155, outputs 18 bitsof data on a data bus (RXData[17:0]). In addition, the output selectioncircuit 155 and the external device, ATM 125, interface through aplurality of control lines, labeled control 155 on FIG. 1.

[0024] The memory blocks (FIFO A 130, FIFO B 135, FIFO C 140, and FIFO D145) each generate a signal (iclav_a, iclav_b, iclav_c, and iclav_d)that indicates whether a cell is available for a read operation in thecorresponding memory block. In general, the arbiter 150 receives thecell available signals (iclav_a, iclav_b, iclav_c, and iclav_d) fromeach memory block (FIFO A 130, FIFO B 135, FIFO C 140, and FIFO D 145),and in return, it controls, based on cell availability, selection of oneof the memory blocks for a read operation. As is explained more fullybelow, the cell available signals (iclav_a, iclav_b, iclav_c, andiclav_d) are transmitted external to the FIFO device 100 to permitexternal selection of a memory block for a read operation. In oneembodiment, the arbiter 150 is implemented as a round robin sequencer.For the round robin sequencer embodiment, the arbiter 150 sequentiallyselects the next memory block with an available cell for a readoperation (e.g. the arbiter 150 selects FIFO A 130, FIFO B 135, FIFO C140, and FIFO D 145 in a sequential order).

[0025] For the embodiment illustrated in FIG. 1, each FIFO block may beprogrammed to operate with a specified number of bytes per cell. In oneembodiment, the cell size is programmed during the initialization orreset when the FIFO device 100 is powered up. Thus, the cell size isdefined for a first write operation to a FIFO memory block. As isexplained more fully below, the FIFO device 100 applies a wide range ofcell sizes for programming during the reset period. In- one embodimentthat includes a nine bit input data bus and an eighteen bit output databus, the write cell size is double the number of bytes per cell of aread cell size because the input data bus receives 9 bits, for the writeoperation, and the output data bus outputs 18 bits for a read operation.For example, if the write cell size is set to 10 bytes per cell, thenthe read cell size is 5 bytes per cell. Thus, each FIFO block isprogrammed after reset of initialization of the FIFO device 100.

[0026]FIG. 2 is a block diagram of a FIFO block configured in accordancewith one embodiment of the present invention. Each FIFO block (FIFO A130, FIFO B 135, FIFO C 140, and FIFO D 145) includes a memory core,labeled 157 on FIG. 2 (e.g. there is one memory core for each FIFOblock). The memory core 157 includes a plurality of cells shown as cells0-n on FIG. 2. In one embodiment, cell sizes are programmed, by a userduring reset, such that the memory core has a variable number of bytesper cell. For this embodiment, all memory cores are programmed toinclude the same number of bytes per cell. For example, if the userspecifies a cell size of 8 bytes per cell, then FIFO A 130, FIFO B 135,FIFO C 140, and FIFO D 145 are all programmed to 8 bytes per cell. Inone embodiment, the cells may be programmed from eight (8) bytes percell to one hundred and twenty eight (128) bytes per cell. For thisembodiment, each memory core includes 128 bytes. If the user specifies acell size of 128 bytes per cell, then the memory core in each FIFO blockincludes 1 cell. Similarly, if the user specifies a cell size of 8 bytesper cell, then the memory core in each FIFO block includes 16 cells.

[0027] As shown in FIG. 2, the memory core 157 receives, on the inputdata bus RXData[8:0], nine-bits of input data for a write operation, andit generates, on an output data bus D[17:0], 18 bits of output data fora read operation. In another embodiment, the output data bus may beexpanded to include the output of more than one FIFO device. Thisembodiment is described more fully below in conjunction with FIG. 11.

[0028] As shown in FIG. 2, each FIFO block (FIFO A 130, FIFO B 135, FIFOC 140, and FIFO D 145) includes, in addition to the memory core 157, awrite variable cell size circuit 300, a read variable cell size circuit400, a memory address circuit 600, and a comparator circuit 160. Ingeneral, the write variable cell size circuit 300 in each FIFO blocksupports the variable cell size by controlling the number of writeoperations in accordance with the specified number of bytes per cell. Asshown in FIG. 2, the write variable cell size circuit 300 receives theexternally generated cell size value (e.g. cell size signal), and inresponse, it generates a byte address. Furthermore, the write variablecell size circuit 300 generates a write cell count for input to thecomparator 160. The memory address circuit 600 generates a memoryaddress during a write operation to a specified cell. In general, thememory address circuit 600 is utilized to byte align write operations toensure predictable data for a subsequent read operation on that cell.The memory address circuit 600 and byte alignment are described morefully below.

[0029] The read variable cell size circuit 400 shown in FIG. 2 receivesthe external cell size value (e.g. cell size signal), and it generates amemory address for a read operation. Specifically, the read variablecell size circuit 400 in each FIFO block supports variable cell sizes bycontrolling the number of read operations in accordance with thespecified number of bytes per cell (e.g. the number of bytes per cellspecified for a write operation). The read variable cell size circuit400 also generates a read cell count for the comparator 160. Thecomparator 160, which receives the read cell count and write cell count,generates a cell available signal (iclav). In general, the cellavailable signals (iclav_[a:d]) is input to the arbiter 150 to controlselection of a FIFO block for a read operation.

[0030] FIFO Block Cell Size Programming

[0031]FIG. 3 is a block diagram illustrating a variable cell sizecircuit to define the number of bytes per cell for an access operationto a cell. The variable cell size circuit may be used for a write or aread operation to memory. As shown in FIG. 3, the variable cell sizecircuit 200 includes a counter 210 and a comparator 220. The comparator220 receives a value, entitled “cell size value”, that defines thenumber of bytes per cell for the corresponding FIFO block. In oneembodiment, the cell size value is a signal generated by the user, andit is input externally to the FIFO device 100 (FIG. 1). The counter 210receives a clock, and for this embodiment, each clock cycle defines anaccess cycle (e.g. read and write operations are executed each clockcycle). The counter 210 generates the byte address for the accessoperation to the current cell. The comparator 220 generates an equal“EQ” signal when the byte address is equal to the cell size value.

[0032] In operation, the counter 210 generates a first byte address,such as (address 0), for a current cell. The comparator compares thebyte address, for the first cell, with the externally input cell sizevalue. During the next access cycle, signified by a new clock cycle, thecounter 210 is incremented and a new byte address is generated. Thiscycle is repeated for each access cycle that the byte address is lessthan the cell size value. When the byte address equals the cell sizevalue, signifying the last byte in the programmed cell size, an active“EQ” signal is generated. In turn, the counter 210 is reset toinitialize the counter for the next cell. Thus, circuitry for the cellsize programming is simplified to include a counter and a comparator.FIG. 3 also includes memory address circuit 600. For this embodiment,the memory address circuit 600 is utilized to generate a memory addressfrom the byte address. One embodiment for the memory address circuit 600is described more fully below in conjunction with FIG. 7.

[0033] In an alternative embodiment, a modulo-N counter (mod counter)may be used to solve the variable cell sizes problem. The mod counter,which transitions through a sequence of counts, may be implemented withflip flops and combination logic. However, the amount of combinationlogic required to implement a variable cell size circuit is increased ifthe FIFO device permits selection of a wide range of cell sizes. Becauseit is desirable to implement a circuit that supports selection of a widerange of cell sizes while minimizing the amount of logic, the variablecell size circuit 200 shown in FIG. 3 is a circuit implementation thatminimizes the amount of logic over the use of a modulo-N counter.

[0034]FIG. 4 illustrates one embodiment of a write variable cell sizecircuit. For the embodiment illustrated in FIG. 4, the write variablecell size circuit 300 contains a counter consisting of an adder 301 anda plurality of counter flip-flops. (318, 320, 322, 324, 326, 328 and330). The counter flip-flops 318, 320 and 322 receive, duringinitialization, a low logic level on the reset pin (e.g. RSL=0) and ahigh logic level on the input (e.g. Q=1). The counter flip-flops 324,326, 328 and 330 receive a low logic level on the reset pin (e.g. RSL=0)and a low logic level on the input (e.g. Q=0). The data Q[6:0] is inputto the adder 301, which in turn, generates data S[6:0]. The data S[6:0]is the sum of 1+Q[6:0]. As shown in FIG. 4, the write variable cell sizecircuit 300 further includes combination logic including AND gates 302,304, 306, 312, 314, and 316, inverters 308, 348, and 350, and a NANDgate 310. The combination logic is used to input values in counterflip-flops (318, 320, 322, 324, 326, 328 and 330) in each reset cellcount operation in the manner discussed above.

[0035] The write variable cell size circuit 300 further includes acomparator 332 and a plurality of prediction flip-flops (334, 336, 338,340, 342, 344, and 346). The prediction flip-flops (334, 336, 338, 340,342, 344, and 346) are D type flip-flops. The comparator 332 receivesdata Q[6:0] and the externally generated cell size value, and itgenerates an active “EQ7” signal when the data value, Q[6:0]), is equalto the cell size value. As shown in FIG. 4, the prediction flip-flops(334, 336, 338, 340, 342, 344, and 346) generate, in addition to the“EQ7” signal, signals “EQ6”, “EQ5”, “EQ4”, “EQ3”, “EQ2”, “EQ1”, and“EQ.” As is described more fully below, the prediction signals are usedto indicate the end of a write or read operation to a cell apredetermined number of cycles prior to the actual completion of thewrite or read operation. Thus, with the prediction mechanism, asubsequent write or read operation may be initiated prior to completionof the write or read operation to the current cell.

[0036] For the write variable cell size circuit embodiment illustratedin FIG. 3, there are seven “7” prediction flip-flops (334, 336, 338,340, 342, 344, and 346). Thus, the combination logic, after an active“EQ” signal is output at flip-flop 346, generates a value of (8)“0001000” for input to the counter flip-flops (318, 320, 322, 324, 326,328 and 330). On the next clock cycle, the output of counter flip-flops,due to the inversion of “EQ” signal to disable the combination logicgates (302, 304, 306, 308, 310, 312, 314, and 316), has a value of “8.”Therefore, the counter flip-flops (318, 320, 322, 324, 326, 328 and 330)are preset to a value of 7, and on the next clock cycle, the counterflip-flops start the count at “8.” Based on this configuration, thevalue of the data Q[6:0] is set to the cell size value seven cyclesprior to the completion of the generation of the active “EQ” signal fromflip-flop 346.

[0037] For each access operation, which is executed in a correspondingclock (CLK) cycle, the adder 301 adds a value of “1” to the data Q[6:0].During an access operation to a cell, the “EQ” signal is a low logiclevel. Therefore, the output of inverter 345 is a high logic level, andthe combination logic (gates 302, 304, 306, 308, 310, 312, 314, and 316)does not affect the input to the counter flip-flops. When the cell sizevalue is equal to Q[6:0], (e.g. seven cycles before the write addressequals the cell size value), the comparator 332 generates an active“EQ7” signal. After the completion of “7” clock cycles, an active “EQ”signal is generated from flip-flip 346. At this time, the inputs tocounter flip-flops (318, 320, 322, 324, 326, 328 and 330) are reset to“00001000”, respectively. After one clock cycle, the counter flip-flopQ3 is set to a “1”, and the value of Q[6:0] is “0001000.” Consequently,the write variable cell size circuit 300, using signal “EQ”, is presetfor a write operation to a new cell.

[0038] For the embodiment shown in FIG. 4, the write variable cell sizecircuit also includes a hard reset function. For this function, thecounter flip-flops (318, 320, 322, 324, 326, 328 and 330) as well as theprediction flip-flops (334, 336, 338, 340, 342, 344, and 346) contain areset input, and the reset signal, RST, is used to reset all flip-flops.Because the flip-flops are reset with a low logic level, the RST signalis input to inverter 350.

[0039]FIG. 5 illustrates one embodiment for a read variable cell sizecircuit. The read variable cell size circuit 400 is used to read cellsfrom a FIFO core, wherein the cell is programmed to have a variablenumber of bytes per cell during the device power up and reset operation.Similar to the write variable cell size circuit illustrated in FIG. 4,the read variable cell size circuit 400 contains a counter that includesan adder 402 and a plurality of counter flip-flops (404, 406, 408, 410,412, and 414). The data output from the counter flip-flops aretransferred on a data bus, labeled Q[5:0] on FIG. 5. The read variablecell size circuit 400 also includes a comparator 416.

[0040] The data from bus Q[5:0] is input to the comparator 416 as afirst input, and the cell size value is input as a second input. Theoutput of comparator 416, “EQ4”, which is set to a high logic level whenthe size value equals the Q[5:0] value, is input to a plurality ofprediction flip-flops (418, 420, 430, and 440).

[0041] As shown in FIG. 5, the output of the counter flip-flops (404,406, 408, 410, 412, and 414) are input to the adder 402. In turn, theadder 402 generates a sum of Q[5:0]+1 for input to the counterflip-flops (404, 406, 408, 410, 412, and 414). For a non resetcondition, the adder 402 output S[5:0] is input to the counterflip-flops (404, 406, 408, 410, 412, and 414). When the cell size valueis equal to the Q[5:0] value, then the comparator 416 generates anactive “EQ4” signal, and an active “EQ” signal is generated four clockcycles later at the output of the prediction flip-flop 440.

[0042] The read variable cell size circuit 400 further includescombination logic to reset the cell count. Similar to the write variablecell size circuit 300, the combination logic includes a plurality of ANDgates (468, 474, 476, and 478) coupled to the D input of counterflip-flops 406, 410, 412 and 414. Also, the combination logic includesan inverter 470 and a NAND gate 472. Furthermore, the combination logicincludes a decoder 450 and a plurality of logic gates (463, 460, 454,458, 456, 462 and 466), to support a read cell size of 4 bytes per cell(i.e. 8 bytes per cell in write mode operation). The decoder 450receives the data Q[5:0], and it generates an internal signal“dec4_cell”.

[0043] If the read cell size equals four, then the dec4_cell signalcauses the XOR gate 462 to act as a buffer and the XOR gate 466 to actas an inverter. Also, the dec4_cell disables the AND gate 468. Two bytesprior to the completion of the count the internal signal “reset_cell” isasserted. The reset_cell signal causes the input of the counterflip-flops (404, 406, 408, 410, 412 and 414) to a value of “00100.”Thus, the counter flip-flops (404, 406, 408, 410, 412 and 414) are setfor the next cell count.

[0044] If the read cell size is greater than four, then the input to thecounter flip-flops (404, 406, 408, 410, 412 and 414) is the same as theinput to the counter flip-flops (318, 320, 322, 324, 326, 328 and 330)of the write variable cell size circuit of FIG. 4, Specifically, XORgate 462 operates as an inverter, and XOR gate 466 operates as a buffer.Also, the signal “reset_celln disables the combination logic (464, 468,472, 474, 476 and 478). The input value to the counter flip-flops (404,406, 408, 410, 412 and 414) is “000101.”

[0045] Byte Alignment in FIFO Cells

[0046] A FIFO device that is configured in accordance with the UTOPIAspecification receives, from each physical device, nine bits for input,and it outputs eighteen bits (e.g. two nine bit bytes) to an outputdevice, such as an ATM device. Therefore, for a read operation, bytesare grouped in two byte pairs such that each read operation reads twobytes that were written in separate write operations. FIG. 6 is a blockdiagram of a cell in a memory core that has been programmed to includenine bytes per cell. For this example, the write variable cell sizecircuit generates nine write addresses WA[8:0] to execute a writeoperation to each byte [8:0] of the cell. To execute a read operationfrom the cell, the read variable cell size circuit 400 generates fiveaddresses RA[4:0], one address for two bytes. For this example, theaddress “RA0” identifies bytes “0” and “1”, the address “RA1” identifiesbytes “2” and “3”, the address “RA2” identifies bytes “4” and ♭5”, theaddress “RA3” identifies bytes “6” and “7”, and the address “RA4”identifies byte “8.” However, since there are-nine bytes per cell, onlyone address, “RA4”, is required to identify one byte, byte “8.”Therefore, an alignment problem occurs in the read operation when an oddnumber of bytes per cell are specified.

[0047] In one embodiment, the FIFO device 100 provides a predeterminedoperation on a byte so that the output of a read operation for a cellhaving an odd number of bytes per cell is predictable. In general, withalignment, all byte positions store data in accordance withpredetermined criteria. For example, in the nine bytes per cell exampleillustrated in FIG. 6, the origin of the contents stored in the tenthbyte position, labeled 500 in FIG. 6, is predefined so that the datacontents is predictable for a standard UTOPIA read using the “RA4”address. In one embodiment to implement alignment, an insertionoperation is utilized. In an insertion operation, the FIFO deviceinserts a copy of the low byte into the high byte position. For the ninebytes per cell example shown in FIG. 6, the contents of byte “8” arecopied into the byte position labeled 500 position for the insertionoperation. Also, alignment is accomplished through a deletion operation.In a deletion operation, the byte being deleted is overwritten by theprevious byte.

[0048] As discussed above, alignment of bytes in a cell may beaccomplished through use of the insertion and/or deletion operations.Table 1 below illustrates example operating modes for a FIFO memory withprogrammable cell sizes. TABLE 1 Cell Cell Byte Insert/Del Size SizeMode Tx/Rx Size BDI Result Range Range 1 x Even 0 No added or 8_128 Cs +0 deleted bytes 2 x Odd 0 Byte insert to 9-127 Cs + 1 last byte position3 Tx Even 1 Delete byte 5 8_128 Cs + 0 Insert last byte 4 Rx Even 1Insert byte 6 8_126 Cs + 2 Insert last byte 5 Tx Odd 1 Delete byte 59-127 Cs − 1 6 Rx Odd 1 Insert byte 6 9-127 Cs + 1

[0049] In one embodiment, the programmable cell size of the FIFO deviceranges between 8 and 128 bytes per cell.

[0050] As shown in Table 1, the FIFO device includes a plurality ofmodes of operation, modes 1-6, for aligning a cell during a writeoperation. For this embodiment, the operation depends upon whether thecorresponding memory core is for receiving or transmitting. The receiveand transmit mode is designated by a signal, RTS. A signal, BDI,indicates a byte insertion or deletion operation for alignment. For thisexample, mode 1 specifies that no bytes are added or deleted. Thus, formode 1, the cell size range is between 8 and 128 bytes per cell, and nocell size adjustment is required. For mode 2, the byte size is odd, andto accomplish byte alignment in this mode, a byte is inserted in thelast byte position. Therefore, for mode 2, the cell size range isbetween 9 and 127 bytes per cell, and the cell size is adjusted by 1(e.g. CS+1). As shown in the additional entries of Table 1, each modespecifies an alignment operation, either deletion, insertion, or bothdeletion and insertion. Note that for insertion and deletion alignmentoperations, the cell size range may be limited. For example, in mode 6,executing an insertion operation on byte 6 limits the cell size rangefrom 9 to 127 bytes per cell.

[0051]FIG. 7 illustrates one embodiment for a byte alignment circuit togenerate a memory address for a write operation. As shown in FIG. 7, thememory address circuit 600 includes a decoder 610, an adder 620, and acounter 630. The memory address circuit 600 receives, at the decoder610, a plurality of address and control signals, and the counter 636generates a memory address for the next write operation to a specifiedcell. For the embodiment discussed above in conjunction with Table 1,the decoder 610 receives the transmit/receive (RTS) signal, the leastsignificant cell size, the insertion/deletion signal (BDI), and a cellcount. The decoder 610, based on a predetermined specification such asthe specification shown in Table 1, generates two control signals, MSEL0and MSEL1. The control signals MSEL1 and MSEL0 control the adder toeither add “0” to the memory address, add “1” to the memory address oradd “2” to the memory address. For a regular write operation (e.g. noalignment is required), the adder 620 adds 1, thereby incrementing thememory address by “1.” For an insertion operation, the adder 620increments by “2” to advance the memory address by two locations. Forthe deletion operation, the adder 620 adds “0” to the memory address,thereby executing the write operation at the same address location asthe prior write operation;

[0052] As shown in FIG. 7, the adder 620 receives the add 0, +1, and +2indications to generate the memory address. Although specific controlsignals are shown input to decoder 610 to implement the specificationshown in Table 1, any criteria may be used to execute an insertion ordeletion operation for alignment without deviating from the spirit andscope of the invention. The output of counter 630, the memory address,is input to the memory core cell to execute a write operation. Thedecoder 610 also receives the memory address to determine the byte forthe next write operation. For example, in mode 3, a deletion operationis executed on byte 5. Thus, the decoder 610 utilizes the memory addressto determine the byte count for that write operation. The decoder 610may be implemented in combination logic.

[0053] Multiplexer Function

[0054] As shown in FIG. 1, each FIFO block (FIFO A 130, FIFO B 135, FIFOC 140 and FIFO D 145) generates a cell available signal, labelediclav_a, iclav_b, iclav_c, and iclav_d, respectively. The arbiter 150utilizes the cell available signals (iclav_a, iclav_b, iclav_c, andiclav_d) to determine if a cell is available in the corresponding FIFO.If a cell is not available for a particular FIFO, then the arbiter 150does not select that FIFO for a read cell operation.

[0055] Also, as shown in FIG. 1, the arbiter 150 generates controlsignals MUX 0, MUX 1, and load multiplexer (LDM). In turn, the outputselection circuit 155 receives the control signals, and through use of amultiplexer, delivers data from the selected FIFO to the ATM 125 via theRX data[17:0] bus.

[0056] In one embodiment, each FIFO block includes a circuit to generatethe corresponding cell available signal (e.g. iclav_a, iclav_b, iclav_c,and iclav_d). The cell available signal is generated through comparisonof a read cell counter and a write cell counter (see FIG. 2). Ingeneral, the read cell counter specifies a cell in the correspondingFIFO for the next read operation. Similarly, the write cell counterdefines a cell for the corresponding FIFO for the next write operation.For example, if a FIFO device includes 20 cells, and the read cell countis set to 19 and the write cell count is set to 20, then an active cellavailable signal is generated to reflect that the device has at leastone available cell for a read operation. Thus, an active cell availablesignal is generated if the write cell count is greater than the readcell count. Note that the read cell count will not be greater than thewrite cell count.

[0057]FIG. 8 is a timing diagram illustrating the loading of a MUX forthe output selection circuit. As shown in FIG. 8, the cell availablesignals (iclav_[a:d]) are active when the signals are a high logiclevel. The load MUX operation utilizes a clock, labeled RCLK on FIG. 8.Furthermore, a timing signal to load the multiplexer, labeled RRSM_CLK,is generated. The arbiter 150 utilizes the RRSM_CLK signal to search foran available cell for a read cell operation. The RRSM_CLK signal isshown as having two cycles on FIG. 8. On the rising edge of the firstcycle, the arbiter 150 utilizes the cell available signals to determinewhether a FIFO device has a cell available. Based on an arbitrationscheme, the arbiter 150, on the rising edge of the second cycle, resetsthe MUX 0 and MUX 1 control signals to select a new FIFO for the readoperation. The arbiter 150 generates the loading MUX (LDM) and the MUX 0and MUX 1 signals. When the LDM signal goes from a low logic level to ahigh logic level, the arbiter 150 searches for the target FIFO. When theLDM goes from a high logic level to a low logic level, the arbiter 150searches for a new MUX to select. FIG. 8 also shows the MUX data, MUX 1and MUX 0, and the transition of new MUX data on the rising edge of theLDM signal.

[0058] As discussed above, in one embodiment, the arbiter 150 utilizes around robin arbitration scheme to select a FIFO among all FIFOs thathave an available cell. Although the present invention is described inconjunction with an arbiter that utilizes a round robin arbitrationscheme, any arbitration scheme may be used without deviating from thespirit and scope of the invention. FIG. 9 is a state diagramillustrating one embodiment for the arbiter 150. Each state in the statediagram corresponds to the state of control signals LDM, MUX 1, and MUX0 (e.g. state 101 signifies LDM=1, MUX 1=0, and MUX 0=1). The binarynumbers that indicate the transitions among states is generated by thecell available signals, wherein the least significant bit is the stateof the iclav_a signal, and the most significant bit is the state of theiclav_d signal. Table 2 includes the states of the MUX signals, MUX 0and MUX 1, for a corresponding FIFO. TABLE 2 MUX 1 MUX 0 Selection 0 0FIFO A 0 1 FIFO B 1 0 FIFO C 1 1 FIFO D

[0059] As shown in Table 2, the MUX signals MUX 1 and MUX 0 indicate theselection of FIFO A when set to “00”, indicate the selection of FIFO Bwhen set to “01”, indicate the selection of FIFO C when set to “10”, andindicate the selection of FIFO D when set to “11.” As shown in FIG. 9,the state diagram indicates the setting of the LDM control signal, andthe MUX 1 and MUX 0 select signals based on the state of the cellavailable signals iclav[a:d]. Note that when all cell available signalsare at a low logic level, data for a new MUX is not loaded. The LDMcontrol signal goes active when there is a MUX to select.

[0060] In one embodiment, a user of the FIFO device 100 may override theoperation of the arbiter 150. For this embodiment, the user receivessignals, CR0-CR3, to indicate which FIFOs have an available cell forreading. In a standard FIFO device, the device provides one bit ofinformation to signify whether any of the FIFO cores have an availablecell. The CR0-CR3 signals are utilized by a user to set up priority andto select a FIFO. With use of the CR0-CR3 signals, a user of the FIFOdevice 100 may determine the exact FIFO that has an available cell.Therefore, external control to select a FIFO memory core for output maybe implemented.

[0061]FIG. 10 illustrates one embodiment for a circuit that receivescell size programming information and that transmits cell availableinformation. As shown in FIG. 10, for each FIFO memory block (FIFO A130, FIFO B 135, FIFO C 140, and FIFO D 145) there is a corresponding Dtype flip-flop (800, 810, 820, and 830) and a correspondingbidirectional driver (840, 850, 860, and 870). For this embodiment, thebidirectional drivers (840, 850, 860, and 870) receive the cell sizeinformation (C_Size0-C_Size3) to specify the cell programminginformation. Also, the bidirectional drivers (840, 850, 860, and 870)transmit the cell available information (CR0-CR3). As shown in FIG. 10,the bidirectional drivers (840, 850, 860, and 870) receive an OEL signalat an OE input. The OEL signal controls the bidirectional drivers toreceive, during reset, the cell size programming information, and totransmit the cell available information for a read operation. In oneembodiment, the bidirectional drivers are coupled to external pins onthe FIFO memory device 100. Thus, for this embodiment, the FIFO device100 includes pins to transmit the cell available information as well asreceive the cell size programming information.

[0062] Expansion of Output Data Bus

[0063] In one embodiment, the output data bus may be expanded bysynchronizing the output data from two or more FIFO devices. FIG. 11illustrates one embodiment for expanding the output data bus. FIG. 11shows two FIFO devices, labeled 700 and 710. For this embodiment, theFIFO device 700 is the master device and the FIFO device 710 is theslave device. Each FIFO device includes MSE and RREN pins. The RREN pincontrols the enabling or disabling of the arbiter 150 for the FIFOdevice. The MSE pin is utilized to determine whether the FIFO deviceoperates as a master or a slave device. The MSE and RREN pins are pulledto a high logic level on the FIFO device 700. For this configuration(e.g. the MSE and RREN pins pulled to a high logic level), the FIFOdevice 700 operates as a master device to expand the output bus, andselection of a FIFO memory core for output is accomplished through theinternal arbiter 150. The MSE and RREN pins on the FIFO device 710 arepulled to a low logic level as shown in FIG. 11. Thus, the FIFO device710 operates as a slave device for expansion of the output data bus, andthe arbiter 150 is disabled such that selection of a FIFO block foroutput is externally controlled.

[0064] In one embodiment, for each FIFO device, an output SOCS signal isgenerated. The SOCS signal indicates validity of data on the output databus. As shown in FIG. 11, the master FIFO device 700 receives data onfour input data busses (DATA_AM[8:0], DATA_BM[8:0], DATA_CM[8:0], andDATA_DM[8:0]), one for each FIFO block. Similarly, the slave FIFO device710 receives data on four separate input data busses (DATA_AS[8:0],DATA_BS[8:0], DATA_CS[8:0], and DATA_DS[8:0]). The master FIFO 700 andslave FIFO 710 include pins for the load MUX (LDM), multiplexer 1 (MUX1) control, and multiplexer 0 (MUX 0) control. For operation in themaster/slave mode, the LDM, MUX 1, and MUX 0 pins are tied together asshown in FIG. 11. The operation of loading the output multiplexer (e.g.output selection circuit 155) and the operation of selecting FIFO blockswithin each device is synchronized (e.g. the multiplexers in both themaster FIFO device 700 and slave FIFO device 710 are loadedsimultaneously). Thus, data for a read operation is outputsimultaneously as indicated by the SOCS signals on both the master andslave FIFO devices 700 and 710.

[0065] In one embodiment, for a single master and a single slave FIFOdevice, the output bus includes, for the master FIFO device 700,Q_M[8:0] and Q_M[17:9]. The slave FIFO device 710 includes, for anoutput data bus, Q_S[8:0] and Q_S[17:9]. Thus, for both the master FIFOdevice 700 and slave FIFO device 710, the output data bus is expanded to36 bits. Each FIFO device includes an enable pin, labeled ENS on masterand slave FIFO devices 700 and 710, to enable the output. The masterFIFO device 700 generates the cell available signal, clavs_m to indicatean available cell. For this embodiment, the cell available signal,clavs_s, is ignored (e.g. the state of the clavs_s signal is a don'tcare condition for the arbiter 150).

[0066] Although the present invention has been described in terms ofspecific exemplary embodiments, it will be appreciated that variousmodifications may be made by those skilled in the art without departingfrom the spirit and scope of the invention as set forth in the followingclaims.

What is claimed is:
 1. A memory device comprising: at least one memorycore comprising a plurality of cells, wherein each memory core supportsconfiguration of a variable number of bytes per cell; a variable cellsize circuit for receiving a cell size value that specifies a number ofbytes per cell and for controlling successive accesses to a cell of saidmemory to support said variable number of bytes per cell, said variablecell size circuit including a counter for generating a count thatspecifies a number of accesses to said cell, and a comparator, coupledto said counter and coupled to receive said cell size value, forcomparing said count with said cell size value, and for resetting saidcounter when said count equals said cell size value.
 2. The memorydevice as set forth in claim 1 , wherein said access operation comprisesa write operation.
 3. The memory device as set forth in claim 2 ,wherein said count from said counter signifies a one byte writeoperation to said memory.
 4. The memory device as set forth in claim 1 ,wherein said access operation comprises a read operation.
 5. The memorydevice as set forth in claim 4 , wherein said count from said countersignifies a two byte read operation from said memory.
 6. The memorydevice as set forth in claim 1 , further comprising a prediction circuitfor indicating completion of access a predetermined number of countsprior to completion.
 7. The memory device as set forth in claim 6 ,wherein: said prediction circuit comprises at least one predictionflip-flop coupled to said comparator for generating an output at leastone count prior to when said count equals said cell size value; and saidcounter comprises a plurality of counter flip-flops, an adder, coupledto receive an output from said counter flip-flops, and combinationlogic, coupled to receive an output of said adder, for generating apreset value for said counter flip-flops to compensate for saidpredetermined number of counts generated in said prediction flip-flops.8. The memory device as set forth in claim 1 , wherein said memorydevice comprises a first-in-first-out memory device.
 9. A circuitcomprising: a memory device comprising a plurality of byte positions forstorage of data, said memory device being configured such that during asingle read operation twice as much data is read than during a singledata write operation, a memory address circuit coupled to said memorydevice for generating successive memory addresses for write operationsto said memory device including for incrementing a memory address bytwo, during a byte insertion operation, and for incrementing a memoryaddress by none for a byte deletion operation to perform byte alignmentfor a memory device that stores an odd number of bytes in accordancewith predetermined criteria.
 10. The circuit as set forth in claim 9 ,wherein said memory address circuit comprises: a decoder, coupled toreceive first control signals that specify said predetermined criteria,for decoding said first control signals to generate a second set ofcontrol signals; an adder coupled to said decoder to receive said secondset of control signals and for generating a single increment output fora normal write operation, for generating a zero increment output for adeletion write operation, and for generating a two increment output foran insertion write operation.
 11. A first-in-first-out (FIFO) memorydevice comprising: a plurality of FIFO memory cores including aplurality of cells, each FIFO memory core including a circuit forgenerating a cell available signal that indicates whether a cell in acorresponding FIFO memory core is available for reading; an arbitercoupled to said FIFO memory cores for receiving said cell availablesignals, for selecting one of said FIFO memory cores, and for generatingcontrol signals that specify and control continuous selection of one ofsaid FIFO memory cores; and an output selection circuit, coupled to saidFIFO memory cores to receive data, and coupled to said arbiter toreceive said control signals, for outputting data as specified by saidcontrol signals.
 12. The first-in-first-out (FIFO) memory device as setforth in claim 11 , wherein said arbiter comprises a round robinsequencer for selecting a FIFO memory core with a cell available in asequential order.
 13. The first-in-first-out (FIFO) memory device as setforth in claim 11 , further comprising a master FIFO memory devicecoupled to a slave FIFO memory device for expanding data output tosynchronize data output from said master FIFO device and said slave FIFOdevice.
 14. The first-in-first-out (FIFO) memory device as set forth inclaim 13 , wherein: said control signals that specify and controlcontinuous selection of one of said FIFO memory cores comprises a loadmultiplexer (LDM) signal, a multiplexer “0” (MUX0) signal, and amultiplexer “1” (MUX1) signal that select data from one of said memorycores and that control output of data selected; and said master FIFOmemory device and said slave memory device comprise a plurality ofexternal pins for coupling said LDM, MUX0, and MUX1 signals tosynchronize output of data for expanding data output.
 15. Afirst-in-first-out (FIFO) memory device comprising: a plurality of FIFOmemory cores, each FIFO memory core including a plurality of cells and acomparator circuit for generating a cell available signal that indicatewhether a cell, in a corresponding memory core, is available forreading; and a plurality of output pins coupled to receive said cellavailable signals, wherein cell available information for each FIFOmemory core is output externally from said FIFO device.
 16. Thefirst-in-first-out (FIFO) memory device as set forth in claim 15 ,further comprising a prediction circuit for generating a predictionsignal for external output that indicates completion of a memory accessa predetermined amount of time prior to actual completion of said memoryaccess.
 17. The first-in-first-out (FIFO) memory device as set forth inclaim 16 , wherein said prediction circuit generates a prediction signalfor external output two cycles prior to completion of said memory accessto said current cell.